1. Field of the Invention
The present invention relates to a semiconductor memory device capable of regulating a difference in bit line load resistance caused depending on the position of a memory element. The semiconductor memory device is used as a non-volatile semiconductor memory device, such as writable EEPROM or EPROM, or the like.
2. Description of the Related Art
Japanese Laid-Open Publication No. 5-198775 discloses a semiconductor memory device capable of regulating a difference in the load resistance of a bit line (hereinafter also simply referred to as bit line load resistance), which is caused depending on the position of a memory element. This device will be described below with reference to FIG. 3.
FIG. 3 is an equivalent circuit diagram showing a memory array structure of a conventional semiconductor memory device.
In FIG. 3, a memory array of the semiconductor memory device comprises: a plurality of virtual ground lines SG (SG1 to SGn, . . . ) arranged in parallel; a plurality of sub-bit lines SB (SB1 to SBn, . . . ) each provided between adjacent virtual ground lines SG; main-bit lines MB (MB1, . . . ) connected to respective groups of sub-bit lines, main ground lines MG (MG1 to MGn, . . . ) each connected to a plurality of virtual ground lines SG; a plurality of word select lines WL (WL0 to WLm, . . . ) provided along a direction crossing the sub-bit line; a plurality of memory cells MC (MC1,1 to MCm,n, . . . ) each provided between a virtual ground line SG and a sub-bit line SB; and switching elements ST (ST1 to STn, . . . ) provided between the main-bit line MB and the sub-bit line SB in the respective bit line groups.
The memory cell MC comprises a MOS transistor, in which the virtual ground line SG is connected to the source terminal, the sub-bit line SB is connected to the drain terminal, and the word select line WL is connected to the gate terminal. Note that the main ground line MG overlaps the memory cell MC in FIG. 3, but the main ground line MG is not connected to the memory cell MC.
The gate terminals of the switching elements ST are connected to respective select signal lines SGT (SGT1 to SGTn, . . . ).
In this memory array, the main-bit line MB and the main ground line MG are made of a metal conductor. The resistance of a conductor is negligible. The sub-bit line SB and the virtual ground line SG have an impurity diffusion region having a higher resistance than that of a metal conductor. Note that the virtual ground line may also be referred to as a sub-bit line, and therefore, will be described below as a source-side sub-bit line SG.
In the memory array of FIG. 3, the total length of the impurity diffusion regions of the drain-side sub-bit line SB and the source-side sub-bit line SG, of a selected memory cell MC, is set to be constant so as to reduce variations in driving current due to the dependency of the driving current on the total conductor resistance.
For example, in FIG. 3, a memory cell positioned on column n selected by the drain-side sub-bit line SBn and the source-side sub-bit line SGn and row m selected by an m-th word line WLm is referred to as MCm,n. In this case, the conductor resistance of the drain-side sub-bit line SBn of the memory cell MCm,n is m×r where r is a resistance per unit cell. On the other hand, the conductor resistance of the source-side sub-bit line SGn is (s−m)×r where s is a distance to a contact C of a sub-bit line (unit: bit). In this case, the total of the resistance of sub-bit lines (the sum of the drain-side and source-side conductor resistances: s×r) is constant.
A memory cell MCm+k,n is located on the same column as that of the memory cell MCm,n (column n) and away by k on a row from the memory cell MCm,n. Between the memory cell MCm+k,n and the memory cell MCm,n, the conductor resistance of the drain-side sub-bit line SBm+k and the conductor resistance of the source-side sub-bit line SGm+k are (m+k)×r and (s−m−k)×r, respectively. Therefore, the sum of these sub-bit line resistances is s×r.
Therefore, according to the above-described conventional technique (Japanese Laid-Open Publication No. 5-198775), even if the position of a memory cell is changed on the same row (position in a row direction), the sum of sub-bit line resistances (s×r) can be constant.
In the above-described conventional technique (Japanese Laid-Open Publication No. 5-198775), the sum of sub-bit line resistances can be a constant value (s×r) in the driving current path of selected memory cells MC. However, the conventional technique has the following problems (1) and (2).
(1) The conductor resistance of the source-side sub-bit lines SG is m×r (m is the row position of a memory cell MC from a contact C of a main ground line MG and a sub-bit line SG), which depends on the position of a memory cell MCm,n. Therefore, when the selected memory cell is driven, the source-substrate potential difference is changed from 0 to m×r (m=0, 1, . . . ). Therefore, the substrate bias effect of the memory cell MCm,n (MOSFET) is changed by a factor of up to m, depending on the address (position) of the memory cell MCm,n.
(2) As the volume of a memory is increased and the width of a conductor is reduced with an improvement in miniaturization and production techniques, variations in resistance due to a difference in position from the main-bit line MB to the sub-bit line SB (position in a lateral direction in FIG. 3) cannot be ignored even when the main-bit line MB is made of a metal conductor. Thus, the resistance cannot be maintained constant.
The above-described problems (1) and (2) lead to the following problems when the memory cell MCm,n is driven.
(1) When the memory cell MCm,n is made of MOSFET, variations in source-substrate potential difference cause the substrate bias effect corresponding to the above-described resistance difference (m−1)×r. As a result, a driving current is reduced. Therefore, particularly in EEPROM or EPROM in which the injection of hot electrons causes data writing, the injection characteristics of hot electrons is deteriorated, so that a program speed varies.
(2) Variations in resistance depending on the path from a main-bit line MB to a sub-bit line SB change a conductor resistance on a driving current path to lead to variations in read or write operations of the memory cell MCm,n depending on the address (position).